The present invention relates to a method of fabricating a semiconductor device having multilayer interconnects.
Recently remarkably developed semiconductor process techniques have enabled super refinement and high integration of interconnects and semiconductor devices, and hence, ULSIs have been largely improved in their performance.
In accordance with improvement in the integration of interconnects, however, the operation speed of a device has become restricted by delay of a signal on an interconnect.
Accordingly, in a ULSI of the 0.25 xcexcm generation or later, SiO2 (with a dielectric constant xcex5 of 4.3) conventionally used as a material for an interlayer insulating film is to be replaced with another material with a smaller dielectric constant, such as SiOF doped with fluorine (xcex5=3.5) and SiO:C including an organic substance (xcex5=2.8 through 3.2) (hereinafter referred to as organic SOG).
Now, a method of fabricating a semiconductor device in which the dielectric constant between interconnects is reduced by using organic SOG disclosed in Japanese Laid-Open Patent Publication No. 9-82799 will be described with reference to FIGS. 34(a) through 34(e).
First, as is shown in FIG. 34(a), an aluminum alloy film with a thickness of 500 nm is deposited on a semiconductor substrate 10, and a first SiOF film (including 6 atom % of fluorine and having a dielectric constant of 3) with a thickness of 200 nm is then deposited on the aluminum alloy film by plasma enhanced CVD. Next, the first SiOF film is patterned into a mask pattern 12 by using a resist pattern as a mask, the resist pattern is then removed, and the aluminum alloy film is patterned into lower-layer interconnects 11 (with a minimum line spacing of 300 nm) by using the mask pattern 12.
Then, as is shown in FIG. 34(b), a second SiOF film 13 (including 6 atom % of fluorine and having a dielectric constant of 3) with a thickness of 100 nm is deposited on the entire surface of the semiconductor substrate 10 by the plasma enhanced CVD. An organic SOG film 14 (having a dielectric constant of 3) with a thickness of 750 nm is then deposited on the second SiOF film 13, and the organic SOG film 14 is locally flattened.
Next, as is shown in FIG. 34(c), the organic SOG film 14 is entirely flattened by CMP using an abrasive of pH 9 including dispersed noncrystal cerium oxide, thereby forming a first interlayer insulating film 14A. In this case, the CMP is carried out until a portion of the organic SOG film 14 above the lower-layer interconnects 11 is removed, but the lower-layer interconnects 11 are never exposed because the second SiOF film 13 works as an etching stopper.
Then, as is shown in FIG. 34(d), a second interlayer insulating film 15 of a silicon oxide film is deposited on the entire surface of the semiconductor substrate 10 by the plasma enhanced CVD.
Thereafter, as is shown in FIG. 34(e), via holes 15a are formed in the second interlayer insulating film 15, and upper-layer interconnects 16 connected to the lower-layer interconnects 11 through the via holes 15a are formed on the second interlayer insulating film 15.
In a semiconductor device fabricated as described above, parasitic capacity between the lower-layer interconnects 11 having the minimum line spacing therebetween is measured, resulting in finding that the dielectric constant is 3 and that the parasitic capacity is small.
The conventional method of fabricating a semiconductor device has, however, the following problems when the line width of the lower-layer interconnect 11 is designed to be the same as the dimension of the via hole 15a and alignment shift is caused in the photolithography for forming the via holes 15a: 
FIG. 35 shows the structure of a via hole 17 formed when the alignment shift is caused. When the alignment is shifted, a portion to be etched is shifted from the upper face of the lower-layer interconnect 11 and the etching proceeds to the second SiOF film 13 and the first interlayer insulating film 14A. Therefore, not only the contact area between the via hole 17 and the lower-layer interconnect 11 is reduced but also the aspect ratio of the via hole 17 is increased. When the aspect ratio of the via hole 17 is increased, a cavity is formed in the upper-layer interconnect 16 during the formation thereof (see FIG. 34(e)), and a gas is generated from the organic SOG film used for forming the first interlayer insulating film 14A. As a result, a via contact defect can be disadvantageously caused.
In consideration of the aforementioned conventional problems, an object of the invention is, in a method of fabricating a semiconductor device designed to have a width of a metal interconnect the same as a dimension of a via hole connected to the upper face of the metal interconnect, preventing position shift of a via contact against the metal interconnect even when alignment shift is caused in a mask pattern used for forming the via hole.
In order to achieve the object, the first method of fabricating a semiconductor device of this invention comprises the steps of successively depositing a first metal film and a first interlayer insulating film on an insulating film formed on a semiconductor substrate; forming a first mask pattern for masking first metal interconnect forming areas on the first interlayer insulating film, and etching the first interlayer insulating film and the first metal film by using the first mask pattern, whereby forming openings in the first interlayer insulating film and forming first metal interconnects from the first metal film; filling a second interlayer insulating film made from a different material from the first interlayer insulating film in the openings of the first interlayer insulating film; forming a second mask pattern having via openings corresponding to via hole forming areas on the first interlayer insulating film and the second interlayer insulating film; etching the first interlayer insulating film by using the second mask pattern under etching conditions that an etching rate for the first interlayer insulating film is higher than an etching rate for the second interlayer insulating film, whereby forming via holes for exposing the first metal interconnects in the second interlayer insulating film; depositing a second metal film on the first interlayer insulating film and the second interlayer insulating film so as to fill the via holes; depositing a third interlayer insulating film on the second metal film; forming a third mask pattern for masking second metal interconnect forming areas on the third interlayer insulating film, and etching the second interlayer insulating film and the second metal film by using the third mask pattern, whereby forming openings in the third interlayer insulating film and forming second metal interconnects from the second metal film; and filling a fourth interlayer insulating film in an interval in the second metal interconnects and in the openings of the third interlayer insulating film.
In the first method of fabricating a semiconductor device, the first interlayer insulating film and the first metal film are etched by using the first mask pattern, so as to form the openings in the first interlayer insulating film and form the first metal interconnects from the first metal film. Therefore, the width of the opening of the first interlayer insulating film accords with the line width of the first metal interconnect. Accordingly, the space in the second interlayer insulating film filled in the openings of the first interlayer insulating film accords with the line width of the first metal interconnect.
Therefore, when the via holes are formed in the second interlayer insulating film by etching the first interlayer insulating film by using the second mask pattern having the via openings under etching conditions that the etching rate for the first interlayer insulating film is higher than the etching rate for the second interlayer insulating film, the dimension of each via hole in the perpendicular direction to the interconnect is smaller than both the dimension of the via opening of the second mask pattern and the line width of the first metal interconnect. Accordingly, in the design where the line width of the first metal interconnect and the dimension of the via hole are the same, the via contact is never shifted from the first metal interconnect even when the alignment shift is caused in the second mask pattern.
In this manner, the increase of the aspect ratio of the via hole can be suppressed in the first method of fabricating a semiconductor device, and hence, no cavity is formed in the via contact. As a result, a contact defect can be prevented from being caused in the via contact.
In the first method of fabricating a semiconductor device, the first interlayer insulating film is preferably made from a material including an inorganic component as a main component, and the second interlayer insulating film is preferably made from a material including an organic component as a main component.
In this manner, the interlayer insulating film including an organic component as a main component and having a small dielectric constant is disposed in the interval in the first metal interconnects, resulting in reducing the capacity between the first metal interconnects. Furthermore, the interlayer insulating film including an inorganic component as a main component and having a good heat conducting property is disposed between the first metal interconnect and the second metal interconnect, resulting in improving a heat releasing property in the first and second metal interconnects. Thus, the etching conditions that the etching rate for the first interlayer insulating film is higher than the etching rate for the second interlayer insulating film can be easily set.
In the first method of fabricating a semiconductor device, the second interlayer insulating film preferably has a smaller dielectric constant than the first interlayer insulating film.
In this manner, the interlayer insulating film having a small dielectric constant is disposed in the interval in the first metal interconnects, resulting in reducing the capacity between the first metal interconnects.
In the first method of fabricating a semiconductor device, the second mask pattern is preferably a hard mask made from a metal material.
In this manner, it is easy to provide the second mask pattern with etching selectivity against the first interlayer insulating film and the second interlayer insulating film. Therefore, the etching conditions that the etching rate for the first interlayer insulating film is higher than the etching rate for the second interlayer insulating film can be easily set.
In the first method of fabricating a semiconductor device, each of the via openings is preferably in a larger plan shape than each of the via holes.
In this manner, even when the alignment shift is caused in the second mask pattern, the dimension of each via contact can be prevented from being smaller than the line width of the first metal interconnect.
The second method of fabricating a semiconductor device of this invention comprises the steps of successively depositing a first metal film and a first interlayer insulating film on an insulating film formed on a semiconductor substrate; forming a first mask pattern for masking first metal interconnect forming areas on the first interlayer insulating film, and etching the first interlayer insulating film and the first metal film by using the first mask pattern, whereby forming openings in the first interlayer insulating film and forming first metal interconnects from the first metal film; filling a second interlayer insulating film made from a different material from the first interlayer insulating film in an interval in the first metal interconnects and in the openings of the first interlayer insulating film; depositing a sacrifice film of an insulating material on the first interlayer insulating film and the second interlayer insulating film; forming a second mask pattern for masking second metal interconnect forming areas on the sacrifice film, and etching the sacrifice film by using the second mask pattern, whereby forming interconnect patterns from the sacrifice film; filling a third interlayer insulating film in an interval in the interconnect patterns; forming a third mask pattern having via openings corresponding to via hole forming areas on the interconnect patterns and the third interlayer insulating film, and etching the interconnect patterns and the first interlayer insulating film by using the third mask pattern under etching conditions that an etching rate for the interconnect patterns is higher than an etching rate for the third interlayer insulating film and that an etching rate for the first interlayer insulating film is higher than an etching rate for the second interlayer insulating film, whereby forming via holes for exposing the first metal interconnects in the second interlayer insulating film; forming interconnect openings in the third interlayer insulating film by removing the interconnect patterns; and filling a second metal film in the via holes of the second interlayer insulating film and in the interconnect openings of the third interlayer insulating film, whereby simultaneously forming via contacts and second metal interconnects from the second metal film.
In the second method of fabricating a semiconductor device, the first interlayer insulating film and the first metal film are etched by using the first mask pattern, so as to form the openings in the first interlayer insulating film and form the first metal interconnects from the first metal film. Therefore, the width of the opening of the first interlayer insulating film accords with the line width of the first metal interconnect, and hence, the space in the second interlayer insulating film filled in the openings of the first interlayer insulating film accords with the line width of the first metal interconnect.
Accordingly, when the via holes are formed in the second interlayer insulating film by etching the first interlayer insulating film by using the third mask pattern having the via openings under etching conditions that the etching rate for the first interlayer insulating film is higher than the etching rate for the second interlayer insulating film, the dimension of each via hole in the perpendicular direction to the interconnect is smaller than both the dimension of the via opening of the third mask pattern and the line width of the first metal interconnect. Accordingly, in the design in which the line width of the first metal interconnect is the same as the dimension of the via hole, the via contact can be prevented from shifting from the first metal interconnect even when the alignment shift is caused in the second mask pattern. Thus, the increase of the aspect ratio of the via hole can be suppressed, resulting in preventing occurrence of a via contact defect.
Furthermore, after forming the interconnect patterns by etching the sacrifice film by using the second mask pattern for masking the second metal interconnect forming area, the third interlayer insulating film is filled in the interval in the interconnect patterns. Therefore, the space in the third interlayer insulating film accords with the width of the second metal interconnect forming area, and hence, the width of each interconnect opening formed in the third interlayer insulating film naturally accords with the width of the second metal interconnect forming area. Accordingly, the second metal interconnects are obtained by filling the second metal film in the interconnect openings of the third interlayer insulating film. Thus, buried interconnects having a dual damascene structure in which each via contact is never shifted from the first metal interconnect can be formed in a self-alignment manner.
In the second method of fabricating a semiconductor device, the first interlayer insulating film is preferably made from a material including an inorganic component as a main component, and each of the second interlayer insulating film and the third interlayer insulating film is preferably made from a material including an organic component as a main component.
In this manner, the interlayer insulating films both including organic components as main components and having small dielectric constants are respectively disposed between the first metal interconnects and between the second metal interconnects, resulting in reducing the capacity between the first metal interconnects and between the second metal interconnects. Also, the interlayer insulating film including an inorganic component as a main component and having a good heat conducting property is disposed between the first metal interconnect and the second metal interconnect, resulting in improving the heat releasing property in the first and second metal interconnects. Furthermore, the etching conditions that the etching rate for the first interlayer insulating film is higher than the etching rate for the second interlayer insulating film can be easily set.
In the second method of fabricating a semiconductor device, the second interlayer insulating film and the third interlayer insulating film preferably have smaller dielectric constants than the first interlayer insulating film.
In this manner, the interlayer insulating films having small dielectric constants are respectively disposed between the first metal interconnects and between the second metal interconnects, resulting in reducing the capacity between the first metal interconnects and between the second metal interconnects.
In the second method of fabricating a semiconductor device, the third mask pattern is preferably a hard mask made from a metal material.
When the third mask pattern is thus a hard mask made from a metal material, it is easy to provide the third mask pattern with the etching selectivity against the first interlayer insulating film and the second interlayer insulating film. Therefore, the etching conditions that the etching rate for the first interlayer insulating film is higher than the etching rate for the second interlayer insulating film can be easily set.
In the second method of fabricating a semiconductor device, each of the via openings is preferably in a larger plan shape than each of the via holes.
In this manner, even when the alignment shift is caused in the third mask pattern, the dimension of each via contact can be prevented from being smaller than the line width of the first metal interconnect.
The third method of fabricating a semiconductor device of this invention comprises the steps of successively depositing a first metal film and a first interlayer insulating film on an insulating film formed on a semiconductor substrate; forming a first mask pattern for masking first metal interconnect forming areas on the first interlayer insulating film, and etching the first interlayer insulating film and the first metal film by using the first mask pattern, whereby forming openings in the first interlayer insulating film and forming first metal interconnects from the first metal film; filling a second interlayer insulating film made from a different material from the first interlayer insulating film in an interval in the first metal interconnects and in the openings of the first interlayer insulating film; successively depositing a second metal film and a third interlayer insulating film on the first interlayer insulating film and the second interlayer insulating film; forming a second mask pattern for masking second metal interconnect forming areas on the third interlayer insulating film, and etching the third interlayer insulating film and the second metal film by using the second mask pattern, whereby forming openings in the third interlayer insulating film and forming second metal interconnects from the second metal film; filling a fourth interlayer insulating film in an interval in the second metal interconnects and in the openings of the third interlayer insulating film; forming a third mask pattern having via openings corresponding to via hole forming areas on the third interlayer insulating film and the fourth interlayer insulating film; etching the third interlayer insulating film by using the third mask pattern under etching conditions that an etching rate for the third interlayer insulating film is higher than an etching rate for the fourth interlayer insulating film, whereby forming via openings in the fourth interlayer insulating film; etching the second metal interconnects by using the third mask pattern, whereby forming via openings in the second metal interconnects; etching the first interlayer insulating film by using the third mask pattern under etching conditions that an etching rate for the first interlayer insulating film is higher than an etching rate for the second interlayer insulating film, whereby forming via holes for exposing the first metal interconnects in the second interlayer insulating film; filling a third metal film in the via holes of the second interlayer insulating film and in the via openings of the second metal interconnect, whereby forming via contacts from the third metal film and connecting the via contacts to the second metal interconnects through the third metal film; and filling a burying insulating film in the via openings of the fourth interlayer insulating film.
In the third method of fabricating a semiconductor device, the first interlayer insulating film and the first metal film are etched by using the first mask pattern, so as to form the openings in the first interlayer insulating film and form the first metal interconnects from the first metal film. Therefore, the width of the opening of the first interlayer insulating film accords with the line width of the first metal interconnect, and hence, the space in the second interlayer insulating film filled in the openings of the first interlayer insulating film accords with the line width of the first metal interconnect.
Accordingly, when the via holes are formed in the second interlayer insulating film by etching the first interlayer insulating film by using the third mask pattern having the via openings under etching conditions that the etching rate for the first interlayer insulating film is higher than the etching rate for the second interlayer insulating film, the dimension of each via hole in the perpendicular direction to the interconnect is smaller than both the dimension of the via opening of the third mask pattern and the line width of the first metal interconnect. Accordingly, in the design in which the line width of the first metal interconnect is the same as the dimension of the via hole, the via contact is never shifted from the first metal interconnect even when the alignment shift is caused in the second mask pattern. Thus, the increase of the aspect ratio of the via hole can be suppressed, resulting in preventing the occurrence of a via contact defect.
Furthermore, after forming the via openings in the second metal interconnects and the via holes in the second interlayer insulating film by using the third mask pattern, the third metal film is filled in the via holes and the via openings, so as to form the contacts and connect the second metal interconnects. Therefore, the via contacts and the second metal interconnects can be simultaneously formed. Thus, buried interconnects having a dual damascene structure in which each via contact is never shifted from the first metal interconnect can be formed in a self-alignment manner, and a semiconductor device having a multilayer interconnect structure including three or more layers can be definitely fabricated by repeating procedures subsequent to the formation of the third mask pattern.
In the third method of fabricating a semiconductor device, the first interlayer insulating film is preferably made from a material including an inorganic component as a main component, and each of the second interlayer insulating film and the fourth interlayer insulating film is preferably made from a material including an organic component as a main component.
In this manner, the interlayer insulating films both including organic components as main components and having small dielectric constants are respectively disposed between the first metal interconnects and between the second metal interconnects, resulting in reducing the capacity between the first metal interconnects and between the second metal interconnects. Also, the interlayer insulating film including an inorganic component as a main component and having a good heat conducting property is disposed between the first metal interconnect and the second metal interconnect, resulting in improving the heat releasing property in the first and second metal interconnects. Furthermore, the etching conditions that the etching rate for the first interlayer insulating film is higher than the etching rate for the second interlayer insulating film can be easily set.
In the third method of fabricating a semiconductor device, the second interlayer insulating film and the fourth interlayer insulating film preferably have smaller dielectric constants than the first interlayer insulating film.
In this manner, the interlayer insulating films having small dielectric constants are respectively disposed between the first metal interconnects and between the second metal interconnects, resulting in reducing the capacity between the first metal interconnects and between the second metal interconnects.
In the third method of fabricating a semiconductor device, the third mask pattern is preferably a hard mask made from a metal material.
In this manner, it is easy to provide the third mask pattern with the etching selectivity against the first interlayer insulating film and the second interlayer insulating film, and hence, the etching conditions that the etching rate for the first interlayer insulating film is higher than the etching rate for the second interlayer insulating film can be easily set.
In the third method of fabricating a semiconductor device, each of the via openings is preferably in a larger plan shape than each of the via holes.
In this manner, even when the alignment shift is caused in the third mask pattern, the dimension of each via contact can be prevented from being smaller than the line width of the first metal interconnect.